The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 2012
Filed:
Aug. 25, 2010
Minsik Cho, Somers, NY (US);
Victor N. Kravets, White Plains, NY (US);
Smita Krishnaswamy, White Plains, NY (US);
Dorothy Kucar, White Plains, NY (US);
Jagannathan Narasimhan, Millwood, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Haifeng Qian, White Plains, NY (US);
Haoxing Ren, Austin, TX (US);
Chin Ngai Sze, Austin, TX (US);
Louise H. Trevillyan, Katonah, NY (US);
Hua Xiang, Ossining, NY (US);
Matthew M. Ziegler, Sleepy Hollow, NY (US);
Minsik Cho, Somers, NY (US);
Victor N. Kravets, White Plains, NY (US);
Smita Krishnaswamy, White Plains, NY (US);
Dorothy Kucar, White Plains, NY (US);
Jagannathan Narasimhan, Millwood, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Haifeng Qian, White Plains, NY (US);
Haoxing Ren, Austin, TX (US);
Chin Ngai Sze, Austin, TX (US);
Louise H. Trevillyan, Katonah, NY (US);
Hua Xiang, Ossining, NY (US);
Matthew M. Ziegler, Sleepy Hollow, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.