The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2012

Filed:

Apr. 22, 2011
Applicants:

Han-hsiang Lee, Taipei, TW;

Yi-cheng Lin, Pingtung County, TW;

Da-jung Chen, Taoyuan County, TW;

Inventors:

Han-Hsiang Lee, Taipei, TW;

Yi-Cheng Lin, Pingtung County, TW;

Da-Jung Chen, Taoyuan County, TW;

Assignee:

Cyntec Co., Ltd., Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A MOSFET pair with a stack capacitor is disclosed herein. It can regulate the input voltage and optimize a short EMI loop. It has a bottom lead frame and an up lead frame, which can simultaneously dissipate the heat generated by two MOSFETs to achieve excellent thermal-dissipation. It can adopt solder, Ag epoxy, or gold balls to implement the electrical bonding of two MOSFETs with the bottom lead frame and the up lead frame to achieve excellent structural flexibility. A device, such as an IGBT, a diode, an inductor, a choke, and a heat sink, can be stacked above the up lead frame to form a powerful SiP module. A corresponding method of manufacturing the MOSFET pair with a stack capacitor is also disclosed herein, which is simple, time-saving, flexible, cost-effective, and facile.


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