Adjusting clock error across a circuit interface

Abstract

A system is provided with clock skew measurement and correction technology. A first circuit or memory controllerincludes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory. One measuring circuit is configured for incremental changing of the phase of a transmitted test data sequence to measure and correct timing of a memory receiver circuit's quadrature clocks based on results of a data comparison of transmitted and received test data. Another measuring circuit is configured to scan a received test data sequence for data transitions to measure and correct timing of a memory transmitter circuit's quadrature clocks based on spacing or timing between detected transitions. Individual memory clock generatorsare controlled with adjustable delay circuitsfor changing phase of different clock signals of the memory to set the clock signals based on the measurements of the controller.