The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2012

Filed:

Jun. 04, 2008
Applicants:

Kun-lung Chen, Taipei, TW;

Shine Chien Chung, Taipei Hsien, TW;

Yung-chin Hou, Taipei, TW;

Yu-chun Wu, Allentown, PA (US);

Inventors:

Kun-Lung Chen, Taipei, TW;

Shine Chien Chung, Taipei Hsien, TW;

Yung-Chin Hou, Taipei, TW;

Yu-Chun Wu, Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.


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