The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 04, 2012

Filed:

Feb. 12, 2010
Applicants:

Kumar Nagarajan, San Jose, CA (US);

S. Gabriel R. Dosdos, San Jose, CA (US);

Dong W. Kim, San Jose, CA (US);

Kong W. Lee, San Jose, CA (US);

Inventors:

Kumar Nagarajan, San Jose, CA (US);

S. Gabriel R. Dosdos, San Jose, CA (US);

Dong W. Kim, San Jose, CA (US);

Kong W. Lee, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.


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