The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2012

Filed:

Apr. 30, 2009
Applicants:

Abhijeet Kolpekwar, Round Rock, TX (US);

Chandrashekar L. Chetput, San Jose, CA (US);

Timothy Martin O'leary, San Jose, CA (US);

Inventors:

Abhijeet Kolpekwar, Round Rock, TX (US);

Chandrashekar L. Chetput, San Jose, CA (US);

Timothy Martin O'Leary, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.


Find Patent Forward Citations

Kolpekwar, Abhijeet. (2012). Using real value models in simulation of analog and mixed-signal systems (U.S. Patent No. 8255191). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8255191

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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