The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2012
Filed:
Jul. 13, 2006
Ken Wadland, Grafton, MA (US);
Randall Lawson, Westford, MA (US);
Jelena Radumilo-franklin, Westford, MA (US);
Ken Wadland, Grafton, MA (US);
Randall Lawson, Westford, MA (US);
Jelena Radumilo-Franklin, Westford, MA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A routing method for a multilayer circuit design layout that has a set of possible preferred local routing directions and a default preferred routing direction for each layer. The method receives a set of user specified constraints on routing directions for particular regions of the design layout. The method tessellates the available routing space into separate tiles and automatically defines a preferred local routing direction for each tile based on the user specified constraints. The set of user specified constraints includes user designated flows, locked etches, 'etch keep-out' areas, user 'planned' data, etc. A routing method for a multilayer design layout that receives a first set of user specified preferred routing directions for particular regions of the multilayer design layout. The method tessellates the available routing space into separate tiles and automatically defines a second preferred local routing direction for each tile based on the user specified preferred routing directions.