The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2012
Filed:
Mar. 22, 2010
Hui-jung Kim, Seoul, KR;
Yong-chul OH, Suwon-si, KR;
Jae-man Yoon, Hwaseong-si, KR;
Hyun-woo Chung, Seoul, KR;
Hyun-gi Kim, Hwaseong-si, KR;
Kang-uk Kim, Seoul, KR;
Hui-Jung Kim, Seoul, KR;
Yong-Chul Oh, Suwon-si, KR;
Jae-Man Yoon, Hwaseong-si, KR;
Hyun-Woo Chung, Seoul, KR;
Hyun-Gi Kim, Hwaseong-si, KR;
Kang-Uk Kim, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
A semiconductor device includes a first transistor, a second transistor, an insulation interlayer pattern and a capacitor. The first transistor is formed in a first region of a substrate. The first transistor has a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar. The second transistor is formed in a second region of the substrate. The insulation interlayer pattern is formed on the first region and the second region to cover the second transistor and expose an upper surface of the pillar. The insulation interlayer pattern has an upper surface substantially higher than the upper surface of the pillar in the first region. The capacitor is formed on the impurity region in the upper portion of the pillar and is electrically connected to the impurity region.