The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Nov. 26, 2008
Applicants:

Albert Ratnakumar, San Jose, CA (US);

Wilson Wong, San Francisco, CA (US);

Jun Liu, Santa Clara, CA (US);

Qi Xiang, San Jose, CA (US);

Jeffrey Xiaoqi Tung, Milpitas, CA (US);

Inventors:

Albert Ratnakumar, San Jose, CA (US);

Wilson Wong, San Francisco, CA (US);

Jun Liu, Santa Clara, CA (US);

Qi Xiang, San Jose, CA (US);

Jeffrey Xiaoqi Tung, Milpitas, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01);
U.S. Cl.
CPC ...
Abstract

Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.


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