The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2012

Filed:

Aug. 02, 2008
Applicants:

Ratnakar Goyal, Delhi, IN;

Naresh Kumar, New Delhi, IN;

Harindranath Parmeswaran, Uttar Pradesh, IN;

Inventors:

Ratnakar Goyal, Delhi, IN;

Naresh Kumar, New Delhi, IN;

Harindranath Parmeswaran, Uttar Pradesh, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment of the invention, a method of analysis of a circuit design is disclosed to generate a statistical timing model. The method includes receiving a timing graph of a circuit including arcs with a statistical function of delay, slew, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; and evaluating the timing pins from input ports to output ports to reduce the timing graph to ease analysis of the reduced timing graph with a processor.


Find Patent Forward Citations

Goyal, Ratnakar. (2012). Methods, systems, and apparatus for variation aware extracted timing models (U.S. Patent No. 8239798). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8239798

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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