The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2012
Filed:
Feb. 08, 2010
Fabrice Verjus, Creully, FR;
Jean-marc Yan-nou, Colomby sur Thaon, FR;
David Chevrie, Bretteville sur Odon, FR;
Francois Lecornec, Luc sur Mer, FR;
Nicolaas J. A. Van Veen, Geldrop, NL;
Fabrice Verjus, Creully, FR;
Jean-Marc Yan-Nou, Colomby sur Thaon, FR;
David Chevrie, Bretteville sur Odon, FR;
Francois LeCornec, Luc sur Mer, FR;
Nicolaas J. A. Van Veen, Geldrop, NL;
Ipdia, Caen, FR;
Abstract
A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.