The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2012

Filed:

Jun. 05, 2008
Applicants:

Hua Wen, Mountain View, CA (US);

Hsiao-ping Tseng, Fremont, CA (US);

Zhong Wang, San Jose, CA (US);

Inventors:

Hua Wen, Mountain View, CA (US);

Hsiao-Ping Tseng, Fremont, CA (US);

Zhong Wang, San Jose, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method is described for routing a semiconductor chip's global nets. The method includes identifying a subset of the global nets and routing the subset of global nets using multiple threads, where, each of the global nets within the subset are routed by one of the threads in isolation of the subset's other global nets. The method further includes identifying a second subset of the global nets and routing the second subset of global nets using the multiple threads, where, each of the global nets within the second subset are routed by one of the threads in isolation of the second subset's other global nets but in respect of the routes of first subset of global nets.


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