The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Dec. 20, 2008
Robert P. Kurshan, New York, NY (US);
Kenneth L. Mcmillan, Berkeley, CA (US);
Robert P. Kurshan, New York, NY (US);
Kenneth L. McMillan, Berkeley, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as 'top-down' design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design.