The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2012

Filed:

Aug. 24, 2010
Applicants:

James William Adkisson, Jericho, VT (US);

Michael Patrick Chudzik, Danbury, CT (US);

Jeffrey Peter Gambino, Westford, VT (US);

Hongwen Yan, Somers, NY (US);

Inventors:

James William Adkisson, Jericho, VT (US);

Michael Patrick Chudzik, Danbury, CT (US);

Jeffrey Peter Gambino, Westford, VT (US);

Hongwen Yan, Somers, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.


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