The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Oct. 28, 2011
Lee-chung LU, Taipei, TW;
Chung-te Lin, Tainan, TW;
Yen-sen Wang, Hsin-Chu, TW;
Yao-jen Chuang, Banciao, TW;
Gwan Sin Chang, Hsin-Chu, TW;
Lee-Chung Lu, Taipei, TW;
Chung-Te Lin, Tainan, TW;
Yen-Sen Wang, Hsin-Chu, TW;
Yao-Jen Chuang, Banciao, TW;
Gwan Sin Chang, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.