The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2012
Filed:
Dec. 01, 2008
Arkadiy Morgenshtein, Kiryat-Motzkin, IL;
Ran Ginosar, Nofit, IL;
Avinoam Kolodny, Haifa, IL;
Eby G. Friedman, Rochester, NY (US);
Arkadiy Morgenshtein, Kiryat-Motzkin, IL;
Ran Ginosar, Nofit, IL;
Avinoam Kolodny, Haifa, IL;
Eby G. Friedman, Rochester, NY (US);
Technion Research & Development Foundation Ltd., Haifa, IL;
Abstract
A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.