The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2012

Filed:

Sep. 12, 2011
Applicants:

Uttam Sengupta, Portland, OR (US);

Prashant Gandhi, Santa Clara, CA (US);

Shobhit Varshney, Jersey City, NJ (US);

Mandar Joshi, Portland, OR (US);

Shreekant Thakkar, Portland, OR (US);

Inventors:

Uttam Sengupta, Portland, OR (US);

Prashant Gandhi, Santa Clara, CA (US);

Shobhit Varshney, Jersey City, NJ (US);

Mandar Joshi, Portland, OR (US);

Shreekant Thakkar, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2006.01); H04B 1/16 (2006.01); H04B 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed.


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