The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2012

Filed:

Dec. 16, 2010
Applicants:

Wen-chiao Ho, Tainan, TW;

Chin-hung Chang, Tainan, TW;

Kuen-long Chang, Taipei, TW;

Chun-hsiung Hung, Hsinchu, TW;

Inventors:

Wen-Chiao Ho, Tainan, TW;

Chin-Hung Chang, Tainan, TW;

Kuen-Long Chang, Taipei, TW;

Chun-Hsiung Hung, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/12 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nphase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)phase is modified to make the data corresponding to the (n+1)phase be the same as the data corresponding to the nphase if the targeted multi-level cells pass a programming verification process according to an nprogramming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.


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