The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2012

Filed:

Dec. 15, 2008
Applicants:

Mark Dydyk, Cave Creek, AZ (US);

Arturo Urquiza, Chandler, AZ (US);

Charles Singleton, Mesa, AZ (US);

Tim Mcintosh, Phoenix, AZ (US);

Inventors:

Mark Dydyk, Cave Creek, AZ (US);

Arturo Urquiza, Chandler, AZ (US);

Charles Singleton, Mesa, AZ (US);

Tim McIntosh, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/46 (2006.01); H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.


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