The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2012

Filed:

Jun. 22, 2010
Applicants:

Robert J. Condon, West Linn, OR (US);

Bryan D. Bowyer, Newberg, OR (US);

Andres R. Takach, Wilsonville, OR (US);

Inventors:

Robert J. Condon, West Linn, OR (US);

Bryan D. Bowyer, Newberg, OR (US);

Andres R. Takach, Wilsonville, OR (US);

Assignee:

Calypto Design Systems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatuses for verifying a concurrent logical design and a corresponding non-sequential algorithmic description are provided. In some implementations, verification of a non-sequential algorithmic description for a device design is facilitated by monitoring a simulation of the non-sequential algorithmic description and synchronizing the timing of selected events with timing from an already completed simulation of a corresponding logical design. With various implementations, the hierarchical blocks in the logical design are monitored during the prior simulation to record selected event information. Subsequently, the recorded event information may be used to synchronize the simulation of the non-sequential algorithmic description.


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