The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2012

Filed:

Apr. 06, 2009
Applicants:

Hideaki Fukuda, Odawara, JP;

Nobuyuki Minowa, Ooi, JP;

Naoki Moritoki, Odawara, JP;

Masanori Takada, Yokohama, JP;

Masato Shimizu, Hiratsuka, JP;

Inventors:

Hideaki Fukuda, Odawara, JP;

Nobuyuki Minowa, Ooi, JP;

Naoki Moritoki, Odawara, JP;

Masanori Takada, Yokohama, JP;

Masato Shimizu, Hiratsuka, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.


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