The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2012
Filed:
Sep. 16, 2009
Jun Liu, Santa Clara, CA (US);
Shankar Sinha, Redwood City, CA (US);
Qi Xiang, San Jose, CA (US);
Yow-juang Liu, San Jose, CA (US);
Jun Liu, Santa Clara, CA (US);
Shankar Sinha, Redwood City, CA (US);
Qi Xiang, San Jose, CA (US);
Yow-Juang Liu, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.