The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2012
Filed:
Apr. 09, 2010
Steven L. Prins, Fairview, TX (US);
Brian K. Kirkpatrick, Allen, TX (US);
Amitabh Jain, Allen, TX (US);
Steven L. Prins, Fairview, TX (US);
Brian K. Kirkpatrick, Allen, TX (US);
Amitabh Jain, Allen, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.