The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Oct. 14, 2008
Xiaojun Wang, Cary, NC (US);
Yuane Qiu, Cupertino, CA (US);
Prasanti Uppaluri, Cary, NC (US);
Judy Huckabay, Fremont, CA (US);
Tianhao Zhang, Raleigh, NC (US);
Xiaojun Wang, Cary, NC (US);
Yuane Qiu, Cupertino, CA (US);
Prasanti Uppaluri, Cary, NC (US);
Judy Huckabay, Fremont, CA (US);
Tianhao Zhang, Raleigh, NC (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Some embodiments provide a method for decomposing a region of an integrated circuit ('IC') design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.