The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Mar. 11, 2008
Richard Leo Galbraith, Rochester, MN (US);
Bruce Alexander Wilson, San Jose, CA (US);
Travis Roger Oenning, Rochester, MN (US);
Mario Blaum, San Jose, CA (US);
Ksenija Lakovic, Menlo Park, CA (US);
Ivana Djurdjevic, San Jose, CA (US);
Richard Leo Galbraith, Rochester, MN (US);
Bruce Alexander Wilson, San Jose, CA (US);
Travis Roger Oenning, Rochester, MN (US);
Mario Blaum, San Jose, CA (US);
Ksenija Lakovic, Menlo Park, CA (US);
Ivana Djurdjevic, San Jose, CA (US);
Hitachi Global Storage Technologies Netherlands, B.V., Armsterdam, NL;
Abstract
A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.