The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Jun. 09, 2010
Yosef Solt, Atzmon-Segev, IL;
Ofir Keren, Moshav Amirim, IL;
Yosef Solt, Atzmon-Segev, IL;
Ofir Keren, Moshav Amirim, IL;
Marvell Israel (M.I.S.L) Ltd., Yokneam, IL;
Abstract
Aspects of the disclosure provide an integrated circuit that is configured for parallel memory testing. The integrated circuit includes a first memory block and a first scrambler coupled to the first memory block during a memory testing. The first memory block includes a first memory array, and a first envelope configured to translate a driving address of the first memory block into a corresponding physical address of the first memory array based on a first memory configuration for using the first memory array. The first scrambler is configured to provide a first plurality of driving addresses and associated first data to the first envelope based on the first memory configuration. The first plurality of driving addresses and the first data are used to test the first memory array according to a first test pattern. Further, the integrated circuit includes a second memory block and a second scrambler coupled to the second memory block during the memory testing. The second memory block includes a second memory array, and a second envelope configured to translate a driving address into a physical address of the second memory array based on a second memory configuration for using the second memory array. The second scrambler is configured to provide a second plurality of driving addresses and associated second data to the second envelope based on the second memory configuration. The second plurality of driving addresses and the second data are used to test the second memory array according to a second test pattern.