The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Sep. 23, 2011
Dennis R. Kling, Milford, MA (US);
Bruce William Chignola, Marlborough, MA (US);
David J. Katz, Andover, MA (US);
Jorge M. Marcial, Marlborough, MA (US);
Leonard Schaper, Fayetteville, AK (US);
Dennis R. Kling, Milford, MA (US);
Bruce William Chignola, Marlborough, MA (US);
David J. Katz, Andover, MA (US);
Jorge M. Marcial, Marlborough, MA (US);
Leonard Schaper, Fayetteville, AK (US);
Raytheon Company, Waltham, MA (US);
Abstract
An improved microelectronic assembly () and packaging method includes a device package for housing a semiconductor die or chip, (), an array of passive electronic components (-) operating in cooperation with the flip chip semiconductor die () and housed inside the device package to decouple noise from input signals, and a heat spreader () disposed between a top surface of the semiconductor die () and a package cover (). The semiconductor die () is configured as a flip chip die and the device package includes a package substrate () configured as a ball grid array. The improved microelectronic device () reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate () and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.