Loop type clock adjustment circuit and test device

Abstract

A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter.