The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2012
Filed:
Mar. 04, 2011
Jiankang Bu, Windham, ME (US);
Henry G. Prosack, Jr., Scarborough, ME (US);
David Courtney Parker, Topsham, ME (US);
Heather Mcculloh, Kennebunk, ME (US);
Jiankang Bu, Windham, ME (US);
Henry G. Prosack, Jr., Scarborough, ME (US);
David Courtney Parker, Topsham, ME (US);
Heather McCulloh, Kennebunk, ME (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage.