The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2012
Filed:
Jan. 09, 2009
Kazuya Sekiguchi, Tokyo, JP;
Yoshio Fukayama, Tokyo, JP;
Yuji Takahashi, Tokyo, JP;
Tomokuni Chino, Tokyo, JP;
Tsuyoshi Kachi, Tokyo, JP;
Katsuhiro Mitsui, Tokyo, JP;
Daisuke Ono, Tokyo, JP;
Tatsuhiko Miura, Tokyo, JP;
Kazuya Sekiguchi, Tokyo, JP;
Yoshio Fukayama, Tokyo, JP;
Yuji Takahashi, Tokyo, JP;
Tomokuni Chino, Tokyo, JP;
Tsuyoshi Kachi, Tokyo, JP;
Katsuhiro Mitsui, Tokyo, JP;
Daisuke Ono, Tokyo, JP;
Tatsuhiko Miura, Tokyo, JP;
Renesas Electronics Corporation, Kawasaki-shi, JP;
Abstract
Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor devices such as power MOSFETs, in particular, trench gate type power MOS devices are formed without having any void since the thickness of aluminum-based electrodes thereof is as large as about 3500 to 5500 nm (2.5 μm or more). In the present invention, a method is provided wherein at the time of forming an aluminum-based electrode metal film positioned over a wafer and having a thickness of 2.5 μm or more over a highland/lowland-repeated region in a line and space form by sputtering, the temperature of the wafer is set to 400° C. or higher and lower than 500° C.