Transistor and method with dual layer passivation

Abstract

Semiconductor devices () and methods (-) are provided with dual passivation layers (). A semiconductor layer () is formed on a substrate () and covered by a first passivation layer (PL-) (). PL-() and part () of the semiconductor layer () are etched to form a device mesa (). A second passivation layer (PL-) () is formed over PL-() and exposed edges () of the mesa (). Vias () are etched through PL-() and PL-() to the semiconductor layer () where source (), drain () and gate are to be formed. Conductors () are applied in the vias () for ohmic contacts for the source-drain () and a Schottky contact () for the gate. Interconnections () over the edges () of the mesa () couple other circuit elements. PL-() avoids adverse surface states () near the gate and PL-() insulates edges () of the mesa () from overlying interconnections () to avoid leakage currents (). An opaque alignment mark () is desirably formed at the same time as the device () to facilitate alignment when using transparent semiconductors ().