The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2012
Filed:
Jul. 17, 2008
Steven Molesa, Sunnyvale, CA (US);
Erik Scher, San Francisco, CA (US);
Patrick Smith, San Jose, CA (US);
Michael Kocsis, San Francisco, CA (US);
Steven Molesa, Sunnyvale, CA (US);
Erik Scher, San Francisco, CA (US);
Patrick Smith, San Jose, CA (US);
Michael Kocsis, San Francisco, CA (US);
Kovio, Inc., San Jose, CA (US);
Abstract
Methods and software for correcting printable circuit layouts. The methods generally including steps of identifying shapes in an input circuit layout, applying a plurality of correction rules to the shapes, and producing an output printed circuit layout in accordance with the identified shapes and the correction rules. The input circuit layout generally comprises a bitmapped image or other description of at least one printable layer of at least one electronic component, device, or die. Embodiments of the present invention further allow for more precise control of spreading and effective coverage of features (e.g., source/drain terminal regions, gates, capacitors, diodes, interconnects, etc.) on a substrate by a printed ink composition including electronic materials.