The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2012
Filed:
Nov. 24, 2009
Sanjay K. Banerjee, Austin, TX (US);
Leonard Franklin Register, Ii, Round Rock, TX (US);
Allan Macdonald, Austin, TX (US);
Dharmendar Reddy Palle, Austin, TX (US);
Emanuel Tutuc, Austin, TX (US);
Sanjay K. Banerjee, Austin, TX (US);
Leonard Franklin Register, II, Round Rock, TX (US);
Allan MacDonald, Austin, TX (US);
Dharmendar Reddy Palle, Austin, TX (US);
Emanuel Tutuc, Austin, TX (US);
Board of Regents, The University of Texas System, Austin, TX (US);
Abstract
A bi-layer pseudo-spin field-effect transistor (BiSFET) is disclosed. The BiSFET includes a first and second conduction layers separated by a tunnel dielectric. The BiSFET transistor also includes a first gate separated from the first conduction layer by an insulating dielectric layer, and a second gate separated from the second conduction layer by an insulating layer. These conduction layers may be composed of graphene. The voltages applied to the first and/or second gates can control the peak current and associated voltage value for current flow between top and bottom conduction channels, and interlayer current voltage characteristic exhibiting negative differential resistance. BiSFETs may be used to make a variety of logic gates. A clocked power supply scheme may be used to facilitate BiSFET-based logic.