The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2012
Filed:
Jan. 26, 2011
Philip A. Stupar, Oxnard, CA (US);
Jeffrey F. Denatale, Thousand Oaks, CA (US);
Robert L. Borwick, Iii, Thousand Oaks, CA (US);
Alexandros P. Papavasiliou, Thousand Oaks, CA (US);
Philip A. Stupar, Oxnard, CA (US);
Jeffrey F. DeNatale, Thousand Oaks, CA (US);
Robert L. Borwick, III, Thousand Oaks, CA (US);
Alexandros P. Papavasiliou, Thousand Oaks, CA (US);
Teledyne Scientific & Imaging, LLC, Thousand Oaks, CA (US);
Abstract
An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.