The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2012

Filed:

Jul. 13, 2010
Applicants:

Ananth Durbha, San Jose, CA (US);

Pius NG, Hillsboro, OR (US);

Gary Oblock, Santa Clara, CA (US);

Suresh Kadiyala, Cupertino, CA (US);

Satish Padmanabhan, Sunnyvale, CA (US);

Inventors:

Ananth Durbha, San Jose, CA (US);

Pius Ng, Hillsboro, OR (US);

Gary Oblock, Santa Clara, CA (US);

Suresh Kadiyala, Cupertino, CA (US);

Satish Padmanabhan, Sunnyvale, CA (US);

Assignee:

Algotochip Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.


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