The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2012

Filed:

Apr. 08, 2010
Applicants:

Nobuyuki Sugii, Tokyo, JP;

Ryuta Tsuchiya, Tokyo, JP;

Shinichiro Kimura, Kunitachi, JP;

Takashi Ishigaki, Hino, JP;

Yusuke Morita, Akishima, JP;

Hiroyuki Yoshimoto, Kawasaki, JP;

Inventors:

Nobuyuki Sugii, Tokyo, JP;

Ryuta Tsuchiya, Tokyo, JP;

Shinichiro Kimura, Kunitachi, JP;

Takashi Ishigaki, Hino, JP;

Yusuke Morita, Akishima, JP;

Hiroyuki Yoshimoto, Kawasaki, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.


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