The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2012
Filed:
May. 23, 2007
Mark Visokay, Richardson, TX (US);
Jorge Adrian Kittl, Waterloo, BE;
Mark Visokay, Richardson, TX (US);
Jorge Adrian Kittl, Waterloo, BE;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (), wherein the NMOS gate structure () includes an NMOS gate dielectric () and an NMOS gate electrode (). This method further includes forming n-type source/drain regions () within the substrate () proximate the NMOS gate structure (), and siliciding the NMOS gate electrode () to form a silicided gate electrode (). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode () prior to or concurrently with siliciding.