The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2012

Filed:

Nov. 17, 2009
Applicants:

Robert Mulfinger, Dresden, DE;

Andy Wei, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Andrew Waite, Dresden, DE;

Inventors:

Robert Mulfinger, Dresden, DE;

Andy Wei, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Andrew Waite, Dresden, DE;

Assignee:

Advanced Micro Devices, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.


Find Patent Forward Citations

Mulfinger, Robert. (2012). Multiple gate transistor having fins with a length defined by the gate electrode (U.S. Patent No. 8183101). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8183101

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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