The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2012

Filed:

Jul. 13, 2010
Applicants:

Chih-chang Lin, San Jose, CA (US);

Chan-hong Chern, Palo Alto, CA (US);

Steven Swei, Fremont, CA (US);

Ming-chieh Huang, San Jose, CA (US);

Tien-chun Yang, San Jose, CA (US);

Inventors:

Chih-Chang Lin, San Jose, CA (US);

Chan-Hong Chern, Palo Alto, CA (US);

Steven Swei, Fremont, CA (US);

Ming-Chieh Huang, San Jose, CA (US);

Tien-Chun Yang, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 13/00 (2006.01); H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.


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