logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8174673 B1

PDFFull Text
Date of Patent:
May. 08, 2012

Filed:

Mar. 18, 2009

Method for wafer alignment

Applicant:

An-hsiung Liu, Taoyuan, TW;

Inventor:

An-Hsiung Liu, Taoyuan, TW;

Assignee:

Nanya Technology Corp., Kueishan, Tao-Yuan Hsien, TW;

Attorneys:

Winston Hsu

Scott Margo

Primary Examiner:

Edward J Glick

Assistant Examiner:

Mesfin T Asfaw

Int. Cl.
CPC ...
G03B 27/42 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for wafer alignment includes the following steps. First, a wafer including a first material layer and a second material layer on the top of the first material layer is provided, wherein the first material layer includes a first alignment mark. Then, the wafer is aligned in an exposure tool. After that, the second material layer is patterned to form a second alignment mark. Finally, an offset distance between the first alignment mark and the second alignment mark is measured in the exposure tool.

Find Patent Forward Citations

Liu, An-Hsiung. (2012). Method for wafer alignment (U.S. Patent No. 8174673). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8174673

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…