The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2012

Filed:

Feb. 15, 2011
Applicants:

Marie Denison, Plano, TX (US);

Taylor Rice Efland, Richardson, TX (US);

Inventors:

Marie Denison, Plano, TX (US);

Taylor Rice Efland, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit () includes one of more transistors () on or in a substrate () having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (). The DEMOS transistor includes a drift region () in the surface layer having a first dopant type, a field dielectric () in or on a portion of the surface layer, and a body region of a second dopant type () within the drift region (). The body region () has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric () is on at least a portion of the body wall. An electrically conductive gate electrode () is on the gate dielectric () on the body wall. A source region () of the first doping type is in the body region (), a drain region () of the first doping type is in the drift region (), and interconnects () are operable to electrically connect the one or more transistors to each other on the integrated circuit ().


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