The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2012

Filed:

Nov. 30, 2009
Applicants:

Eun-ji Jung, Suwon-si, KR;

Hyun-soo Kim, Gwacheon-si, KR;

Byung-hee Kim, Seoul, KR;

Dae-yong Kim, Yongin-si, KR;

Woong-hee Sohn, Seoul, KR;

Kwang-jin Moon, Suwon-si, KR;

Jang-hee Lee, Yongin-si, KR;

Min-sang Song, Seongnam-si, KR;

Eun-ok Lee, Hwaseong-si, KR;

Inventors:

Eun-ji Jung, Suwon-si, KR;

Hyun-soo Kim, Gwacheon-si, KR;

Byung-hee Kim, Seoul, KR;

Dae-yong Kim, Yongin-si, KR;

Woong-hee Sohn, Seoul, KR;

Kwang-jin Moon, Suwon-si, KR;

Jang-hee Lee, Yongin-si, KR;

Min-sang Song, Seongnam-si, KR;

Eun-ok Lee, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.


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