The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2012
Filed:
Oct. 20, 2008
Matthew T. Herrick, Cedar Park, TX (US);
Ko-min Chang, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Matthew T. Herrick, Cedar Park, TX (US);
Ko-Min Chang, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.