The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2012

Filed:

Mar. 17, 2010
Applicants:

In-sang Jeon, Gyeonggi-do, KR;

Si-hyung Lee, Gyeonggi-do, KR;

Jong-ryeol Yoo, Gyeonggi-do, KR;

Yu-ghun Shin, Gyeonggi-do, KR;

Suk-hun Choi, Gyeonggi-do, KR;

Inventors:

In-Sang Jeon, Gyeonggi-do, KR;

Si-Hyung Lee, Gyeonggi-do, KR;

Jong-Ryeol Yoo, Gyeonggi-do, KR;

Yu-Ghun Shin, Gyeonggi-do, KR;

Suk-Hun Choi, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.


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