The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2012
Filed:
Apr. 15, 2009
Yuan-sun Chu, Minsyong Township, Chiayi County, TW;
Yi-ren Chen, Kaohsiung, TW;
Chia-ying Huang, Kaohsiung, TW;
Chi-fang LI, Minsyong Township, Chiayi County, TW;
Yuan-Sun Chu, Minsyong Township, Chiayi County, TW;
Yi-Ren Chen, Kaohsiung, TW;
Chia-Ying Huang, Kaohsiung, TW;
Chi-Fang Li, Minsyong Township, Chiayi County, TW;
National Chung Cheng University, Chia-Yi, TW;
Abstract
The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.