The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2012
Filed:
Dec. 28, 2005
Srikrishnan Venkataraman, Bangalore, IN;
Jayashree Kar, Saratoga, CA (US);
Sudarshan D. Solanki, Bangalore, IN;
Priyavadan Ramdas Patel, Bangalore, IN;
Michael M. Desmith, Beaverton, OR (US);
David G. Figueroa, Tolleson, AZ (US);
Srikrishnan Venkataraman, Bangalore, IN;
Jayashree Kar, Saratoga, CA (US);
Sudarshan D. Solanki, Bangalore, IN;
Priyavadan Ramdas Patel, Bangalore, IN;
Michael M. DeSmith, Beaverton, OR (US);
David G. Figueroa, Tolleson, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time 'T' of the lanes is determined. The number of lanes 'N' in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.