The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2012
Filed:
Jun. 11, 2010
Richard Booth, Riegelsville, PA (US);
Paulius Mosinskis, Richlandtown, PA (US);
Phillip Johnson, Hellertown, PA (US);
David Onimus, Drexel Hill, PA (US);
Richard Booth, Riegelsville, PA (US);
Paulius Mosinskis, Richlandtown, PA (US);
Phillip Johnson, Hellertown, PA (US);
David Onimus, Drexel Hill, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFFto an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF-COEFF) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.