Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices

Abstract

An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding the metal interconnect. A second interlayer dielectric layer of a predetermined thickness is overlying the first interlayer dielectric layer. A trench opening of a first width is formed within an upper portion of the second interlayer dielectric layer. A first barrier layer is within and is overlying the trench opening of the first width. A contact opening of a second width is within a lower portion of the second interlayer dielectric layer. The second width is less than the first width. The lower portion of the second interlayer dielectric layer is coupled to the upper portion of the second interlayer dielectric layer within the predetermined thickness of the second interlayer dielectric. A second barrier layer is within and is overlying the opening of the contact opening and overlying the first barrier layer. A directional partially or completely removal of the second barrier forming a low contact resistance structure. A copper material is formed overlying the first barrier layer and the second barrier layer to substantially fill the contact opening and the trench within the second interlayer dielectric layer.