The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2012
Filed:
Nov. 16, 2009
Ken Wadland, Grafton, MA (US);
Richard Woodward, San Diego, CA (US);
Randall Lawson, Westford, MA (US);
Greg Horlick, Madison, AL (US);
Ken Wadland, Grafton, MA (US);
Richard Woodward, San Diego, CA (US);
Randall Lawson, Westford, MA (US);
Greg Horlick, Madison, AL (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. An automatic evaluation is then made of the potential impact upon constraint compliance. The evaluation includes generating a relative cost measure for the preliminary modification of the circuit routing solution, based at least partially upon each of the constraint instances. Thereafter, the preliminary modification of said circuit routing solution is either discarded or accepted responsive to the evaluation. A number of these operations may be repeated in recursive manner, if appropriate for the given application.