The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2012

Filed:

Oct. 08, 2009
Applicants:

Jonghae Kim, San Diego, CA (US);

Shiqun Gu, San Diego, CA (US);

Brian Matthew Henderson, Escondido, CA (US);

Thomas R. Toms, San Diego, CA (US);

Lew G. Chua-eoan, Carlsbad, CA (US);

Seyfollah S. Bazarjani, San Diego, CA (US);

Matthew Nowak, San Diego, CA (US);

Inventors:

Jonghae Kim, San Diego, CA (US);

Shiqun Gu, San Diego, CA (US);

Brian Matthew Henderson, Escondido, CA (US);

Thomas R. Toms, San Diego, CA (US);

Lew G. Chua-Eoan, Carlsbad, CA (US);

Seyfollah S. Bazarjani, San Diego, CA (US);

Matthew Nowak, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.


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